1. Field of the Invention
The invention generally relates to on-chip data interfaces, and in particular to integrated circuit chips having circuit units that may interchange requests and responses.
2. Description of the Related Art
Integrated circuit chips are often used for data processing and are known to comprise a number of different circuit units. Generally, each circuit unit is for performing a specific function and of course, there may be different circuit units provided on one chip for performing different functions. The circuit units may operate sequentially or simultaneously, and they may function independently from each other, or dependent on the operation of other circuit units.
In the latter case, the circuit units are usually inter-connected via an interface to allow the circuit units to interchange data needed for making the operation of one circuit unit dependent on the operation of the other circuit unit. The data exchange is often done by sending transactions from one circuit unit to the other circuit unit. A transaction is a sequence of packets that are exchanged between the circuit units and that result in a transfer of information. The circuit unit initiating a transaction is called the source, and the circuit unit that ultimately services the transaction on behalf of the source is called target. It is to be noted that there may also be intermediary units between the source and the target.
Transactions may be used to place a request, or to respond to a received request. Taking the requests, there may be distinguished posted request from non-posted requests, dependent on whether the request requires a response. Specifically, a non-posted request is a request that requires a response while a posted request does not require a response.
When focusing on the functions which are performed by the inter-connected circuit units, the circuit units can often be divided into hosts and devices. The term host then means a circuit unit that provides services to the dependent device. A transaction from the host to the device is said to be downstream, while a transaction in the other direction is said to be upstream. In bi-directional configurations, both the host and the device may send and receive requests and responses so that a device may be a source as well as target, and also the host may function as source as well as a target.
A field where such integrated circuit chips are widely used are personal computers. Referring to FIG. 1, the hardware components of a common motherboard layout are depicted. It is to be noted that this figures shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard of FIG. 1 include the CPU (Central Processing Unit) 100, a northbridge 105, a southbridge 110, and system memory 115. The northbridge 105 usually is a single chip in a core-logic chipset that connects the processor 100 to the system memory 115 and, e.g., to the AGP (Accelerated Graphic Port) and PCI (Peripheral Component Interface) buses. The PCI bus is commonly used in personal computers for providing a data path between the processor 100 and peripheral devices like video cards, sound cards, network interface cards and modems. The AGP bus is a high-speed graphic expansion bus that directly connects the display adapter and system memory 115. AGP operates independently of the PCI bus.
The southbridge 110 is usually the chip in a system core-logic chipset that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus, the USB (Universal Serial Bus), that provides plug-n-play support, controls the PCI-ISA (Industry Standard Architecture) bridge, manages the keyboard/mouse controller, provides power management features, and controls other peripherals.
Thus, common personal computers include southbridges 110 which are integrated circuit chips substantially as described above. To satisfy the demands for high-speed chip-to-chip communication to and from the southbridge 110, the HyperTransport™ technology was developed which provides a high-speed, high-performance point-to-point on-board link for interconnecting integrated circuits on a motherboard. It can be significantly faster than a PCI bus for an equivalent number of pins. The HyperTransport technology is designed to provide significantly more bandwidth than current technologies, to use low-latency responses, to provide low pin count, to be compatible with legacy computer buses, to be extensible to new system network architecture buses, to be transparent to operating systems, and to offer little impact on peripheral drivers.
While the HyperTransport interface thus provides a high-speed chip-to-chip interface, data processing performed within the chips itself may often become the bottle neck. Thus, there is a problem in the prior art that the full performance provided by on-board interchip interfaces such as the HyperTransport interface cannot be brought down to the peripherals since the on-chip interfaces in intermediate integrated circuit chips decrease the overall performance.